IIIT-Delhi
Indraprastha Institute of Information Technology, Delhi
IIIT-Delhi PhD (ECE) Admission 2012
Entrance Test Details for PhD (ECE)
How to Apply
Fill up the online application form.
Last date of application - May 25, 5:00P.M. (Friday).
Send a demand draft of non-refundable Rs 350/- towards application processing fee in favour of IIIT-Delhi payable in New Delhi to the following address:
PhD Admission Committee
IIIT-Delhi
3rd Floor, Library building, NSIT Campus
Azad Hind Fauj Marg
Sector-3, Dwarka
New Delhi - 110078
The draft should reach IIIT-Delhi latest by May 28, 5:00P.M.; otherwise your application might be rejected without screening.
The candidates will be screened based on the information provided in the online application form.
Entrance Test
The shortlisted candidates will have to appear for a written test and interviews at IIIT-Delhi on June 10th.
Entrance test details:
Reporting date: June 10, 2012
Registration time: 7:30 A.M
Written test starts: 9:00 A.M.
Students will have to bring all the documents supporting the facts in their application form, e.g., certificates, mark-sheets, publications etc.
Written Test
Written test: The written test will have two sections (Part A and B) as described below. The questions will be on standard B.Tech. level concepts. Syllabus for the testis given below.The questions may be a mixture of multiple choice, fill in the blanks, one-two line answers, and similar short answers. They will not require long descriptive answers. Use of calculators and similar computing devices will not be permitted.
Part-A is compulsory. This section will have questions from circuit theory, calculus and probability.
Syllabus:
Calculus: Mean value theorems, Theorems of integral calculus, Maxima and minima, First order differential equation (linear and nonlinear), Initial and boundary value problems
Probability: Conditional probability, Random variables, Discrete and continuous distributions, Poisson, Normal and Binomial distribution, Circuits:Thevenin and Norton's maximum power transfer, Wye-Delta transformation. Time domain analysis of simple RLC circuits, Solution of network equations using Laplace transform: frequency domain analysis of RLC circuits.
In Part-B, candidates need to choose ANY ONE from the following 3 subsections. The candidate will have to specify their choice during registration on the morning of the test.
Digital Circuits.
Syllabus:
Boolean algebra, minimization of Boolean functions; logic gates; digital IC families (DTL, TTL, ECL, MOS, CMOS). Combinatorial circuits: arithmetic circuits, multiplexers, decoders, PROMs and PLAs. Sequential circuits: latches and flip-flops,
counters and shift-registers. Sample and hold circuits, ADCs, DACs. Semiconductor memories. Microprocessor: architecture, programming, memory and I/O interfacing.
Analog Circuits
Syllabus:
Analog Circuits: Small Signal Equivalent circuits of diodes, BJTs, MOSFETs and analog CMOS. Simple diode circuits, clipping, clamping, rectifier. Biasing and bias stability of transistor and FET amplifiers. Amplifiers: single-and multi-stage, differential and operational, feedback, and power. Frequency response of amplifiers. Simple op-amp circuits. Filters. Sinusoidal oscillators; criterion for oscillation; single-transistor and op-amp configurations. Function generators and wave-shaping circuits, 555 Timers. Power supplies.
Communication Systems
Syllabus:
Random signals and noise: probability, random variables, probability density function, autocorrelation, power spectral density. Analog communication systems: amplitude and angle modulation and demodulation systems, spectral analysis of these operations, signal-to-noise ratio (SNR) calculations for amplitude modulation (AM) and frequency modulation (FM) for low noise conditions.Digital communication systems: pulse code modulation (PCM), differential pulse code modulation (DPCM), digital modulation schemes: amplitude, phase and frequency shift keying schemes (ASK, PSK, FSK), matched filter receivers, bandwidth consideration and probability of error calculations for these schemes. Basics of TDMA, FDMA and CDMA and GSM.
Interview
Shortlisted candidates (after the written test) will be interviewed on the same day.
Apart from general problem solving questions, interview MAY also involve writing small code in C, Verilog/VHDL or microcontroller programming.
A final shortlist, based on (i) the performance in the tests, (ii) the interview, (iii) the background and (iv) references will be the final list of admitted candidates.
The admission decisions (i.e. screening, shortlisting, and others) will be made by the IIIT-D PhD Admission Committee, which will be final.
For complete details on the course, application form, eligibility, prospectus etc visit IIIT-Delhi website
